1. Field of the Invention
The present invention relates to the field of electronic circuits, and more particularly, to phase-locked loop circuits, which may be used in a variety of computer system applications and electronic circuit applications.
2. Art Background
A typical prior art phase-locked loop (PLL) circuit is comprised of a phase and frequency detector, a low-pass filter, and a voltage controlled oscillator. The phase and frequency detector (PFD) compares two input signals, a reference signal and a feedback signal, and generates a phase error signal that is a measure of their phase difference. The phase error signal from the PFD is filtered by the low-pass filter and fed into the control input of the voltage controlled oscillator (VCO). The VCO generates a periodic signal with a frequency controlled by the filtered phase error signal. The VCO output is coupled to the feedback input of the PFD, thereby forming a feedback loop. The feedback loop may contain other components such as clock buffers or clock distribution networks. If the frequency of the feedback signal is not equal to the frequency of the reference signal, the filtered phase error signal causes the VCO frequency to deviate toward the frequency of the reference, until the VCO finally "locks" onto the frequency of the reference signal.
Applications for PLL circuits are many and varied. They include clock circuits for high speed computer systems, tone decoding, demodulation of AM and FM signals, frequency multiplication, frequency synthesis, and pulse synchronization of signals from noisy sources.
However, prior art PLL circuits are unreliable under conditions that cause the VCO control to be abnormally high. System power-up or reset can cause the VCO control to go higher than normal. This condition may also occur when the system returns from test mode. A higher than normal VCO control results in higher than normal VCO frequency, which can cause reduced loop gain because components in the loop may not be able to distribute a high frequency signal. The distribution network can severely attenuate the signal to the point where the feedback signal is not detected the PFD. As a consequence, the VCO may run faster as the normal response to a high control, or the VCO may stall. In either case, the PFD detects the large difference in frequency between the reference and feedback signals and increases the VCO control, which causes an increase in the VCO frequency and thereby worsens the problem.
Moreover, the standard digital PFD used in some prior art PLL circuits is vulnerable to an internal race condition during PFD reset. The standard edge triggered lead-lag digital PFD is composed of logic gates that are interconnected to form a set of four latches, two latches in the lead portion of the PFD and two latches in the lag portion. A PFD reset gate resets all four latches after the PFD has sampled the reference and feedback signals. The standard prior art PFD reset gate is a four input NOR logic gate. Two inputs to the PFD reset gate indicate that the latches in the lead portion of the PFD have reset, while the remaining two inputs indicate that the latches in the lag portion have reset. The PFD reset signal is asserted when all four inputs to the PFD reset gate are low. However, if any one of the four inputs goes high the PFD reset de-asserts. It can be appreciated that if one portion of the PFD is faster than the other, the PFD reset will de-assert before both portions have reset. This can cause the PFD to miss the next cycle of the reference or feedback signals and fail to detect their phase difference.
A common method of guarding against this race condition is to add extra gates to the output of the PFD reset gate in order to widen the pulse width of the reset signal, in the hope that both portions of the PFD will reset during the extra reset time. However, a wider reset pulse does not guarantee that both portions of the PFD will reset during the expanded reset time; it just makes it more likely. Also, increasing the reset pulse reduces the capture range of the PFD since the reference and feedback signals cannot be sampled during reset.
As will be described, the present invention overcomes problems associated with prior art PLL circuits by providing a hyperactivity detection and correction circuit that corrects an abnormally high VCO control, and a PFD reset gate that is not vulnerable to the internal race condition described above.